This invention relates to a semiconductor memory device, and principally to a technique which is effective for use in effecting defect relief in a dynamic RAM (Random Access Memory).
A defective bit-free chip cannot be formed any more in a semiconductor memory device in which attempts have been made to achieve mass storage capacities such as 64 Mbits, 256 Mbits, etc. It is essential for redundant circuits for switching faulty or defective word lines or bit lines to spare word lines or bit lines, respectively, to be provided for such a semiconductor memory device. In this case, fuses have been used to store faulty or defective addresses. However, in a configuration wherein fuses are provided in one-to-one-correspondence with complementary address signals comprised of "true (True)" and "bar (Bar)" signals and one of them is rendered open to store defective addresses, a vast number of fuses are needed, thus resulting in an undesirable increase in the chip size. If the number of the fuses is restricted to avoid an undue increase in the chip size, then a problem arises in that the efficiency of relief is sacrificed.
Various redundant circuits using fuses have been described in Japanese Patent Application Laid-Open Nos. 6295592, 9-7389 and 8-77791.